Identify and recruit high-impact talent for Supply Chain, Procurement, Planning, Manufacturing Operations, and Logistics functions. Partner with hiring managers to scope roles and build scalable recruiting workflows to support company growth.
Tenstorrent
25 Remote Job Openings at Tenstorrent
Define the architecture for next-generation chiplet-based compute platforms and high-performance RISC-V CPUs. Own key platform subsystems including PCIe, die-to-die connectivity, and confidential computing while collaborating with cross-functional teams.
Own the end-to-end electronics components and PCB supply chain, managing relationships with contract manufacturers and distributors. Ensure supply base scalability and resilience from BOM creation to final board delivery while aligning production forecasts with capacity.
Design, document, and improve end-to-end supply chain workflows across procurement, planning, logistics, and manufacturing. Partner with functional leads to translate business needs into ERP configurations and manage master data quality.
Implement and verify DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs. Collaborate with RTL, physical design, and verification teams to ensure testability and automate DFT flows using industry-standard EDA tools.
Field Application Engineer - AI Software & Hardware
Tenstorrent
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Full Time
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17 days ago
Tenstorrent
Collaborate with sales teams and enterprise customers to drive the adoption of AI products and solutions. Provide technical guidance through meetings and workshops while feeding customer insights back to product teams to shape the roadmap.
Act as a hybrid Chief of Staff and TPM to define goals and drive execution for the RISC-V software organization. Manage operational visibility, headcount planning, and cross-functional initiatives to resolve bottlenecks.
Drive microarchitecture and RTL development for digital IPs powering AI/ML accelerators and CPUs. Manage the full lifecycle from design and debug to test and silicon bring-up.
Develop cutting-edge die-to-die chiplet PHY IP solutions and analog/mixed-signal blocks in deep sub-micron FinFET technologies. Manage the full silicon lifecycle from design and verification to tape-out and production-quality bring-up.
Manage supplier performance regarding cost, quality, and delivery while driving cost reduction initiatives. Identify supply chain risks early and implement mitigation plans in partnership with engineering and logistics teams.
The role involves integrating and optimizing low-level kernel infrastructure for RISC-V processors while leading the development of a native agentic AI software stack. You will collaborate with CPU architects and compiler engineers to ensure software capabilities align with RISC-V architectural features.
The Regional Sales Lead will own client relationships while identifying and developing new business opportunities across the AI and compute landscape. They will collaborate with cross-functional teams to execute sales strategies and deliver against revenue targets.
The role involves leading the definition and development of fully enabled software stacks for ADAS, IVI, and robotics domains across various processors and accelerators in heterogeneous edge computing environments. This includes defining and coordinating how software will enable the next generation of open compute architectures across domains and partners.
The Site Manager will guide program planning and execution for major silicon and platform initiatives, acting as the key bridge between German engineering efforts and global priorities. This includes establishing and growing Munich as a high-impact innovation hub by shaping technical direction and driving execution for next-generation compute technology.
The engineer will be responsible for building, packaging, and releasing the software that enables customers to succeed with RISC-V and system IP products. This involves combining Linux and various open-source packages with proprietary software to accelerate customer use of the IP.
The engineer will build the infrastructure necessary for exploring, testing, and validating chiplet-based systems across hardware, software, and architectural layers. This involves creating a scalable, high-performance emulation ecosystem to support debug, software development, and power/performance analysis for SiP based AI/ML engines.
This role involves leading verification efforts on state-of-the-art digital designs, owning the verification strategy, building advanced test environments, and mentoring engineers to ensure functional and performance quality. The engineer will help shape verification for compute engines powering AI and high-performance computing.
The role involves architecting and specifying one or more chiplets intended for robotics and automotive applications, translating high-level requirements into detailed architectural direction. This includes identifying impactful features that enhance Power, Performance, Area (PPA), safety, and reliability while collaborating across design, verification, and software teams.
The role involves defining the test strategy for multi-chiplet packages from initial silicon through high volume production, coordinating test, yield, and quality efforts across multiple teams and companies. Responsibilities also include feeding lessons learned back into next-generation SiP architectures, DFT strategy, and test content.
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Tenstorrent
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5 months ago
Tenstorrent
The engineer will lead the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII, focusing on closing high-speed D2D interfaces for multi-die/chiplet architectures. This includes owning the full PD flow, driving timing and verification sign-off, and improving physical design methodologies.
The designer will help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications, contributing to current datacenter networking efforts while seeding future low-power robotics/automotive devices. This involves working at the intersection of NoC, performance modeling, and RTL design to guide architectural decisions for AI/ML compute and sensor ingest.
RISC-V AI / HPC & Agentic Software Engineering Lead
Tenstorrent
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Full Time
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5 months ago
Tenstorrent
This role is responsible for integrating and optimizing the Low-Level Kernel (LLK) infrastructure for CPU execution while leading the bring-up of a RISC-V-native agentic AI software stack. The lead will collaborate closely with architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.
The engineer will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, directly influencing performance, power, and area outcomes on advanced process nodes. This involves designing and integrating multiple chiplets into a System-in-Package (SiP) while collaborating globally.
As an Automotive and Robotics SoC Architect, you will define scalable, top-down system architectures that unify CPU and AI technologies for next-generation automotive applications. This role shapes the architectural direction of the automotive and robotics portfolio, ensuring products meet high expectations for performance, safety, reliability, and security.
Lead the growth of the RISC-V software ecosystem and expand the software team to establish RISC-V as the industry standard. Engage in innovative projects within a dynamic, collaborative setting while contributing to open-source communities.
