You will build strategic customer relationships and identify new business opportunities to grow Tenstorrent's presence in the autonomy and robotics sectors. You will also partner with cross-functional teams to execute regional business strategies and communicate the value of AI compute solutions to clients.
The engineer will lead verification efforts for complex digital designs, including defining strategies and building advanced test environments. They will also mentor junior engineers and collaborate with cross-functional teams to ensure high-quality, functional compute engines.
Serve as the technical bridge between Tenstorrent and customers in Southeast Asia by guiding technical evaluations, deployments, and troubleshooting. Build and maintain regional relationships while providing hands-on technical support for AI/ML hardware and software solutions.
You will optimize software workloads across datacenter and agentic AI platforms by identifying performance bottlenecks and developing hardware-aware solutions. This involves working across compilers, runtimes, and CPU microarchitecture to improve throughput, latency, and efficiency on RISC-V silicon.
The Formal Verification Engineer will ensure the correctness of high-performance RISC-V CPUs and AI compute platforms using formal methods. They will collaborate with architects and RTL designers to develop properties, build verification environments, and drive failure resolution.
You will partner with senior leaders to manage organizational design, performance calibration, and sensitive employee matters during a period of rapid growth. You will own HR problems from start to finish and help build the People function's systems and practices.
The engineer will characterize and analyze datacenter and agentic AI workloads on RISC-V platforms to identify performance bottlenecks. They will collaborate with hardware and software teams to translate these insights into architectural improvements for next-generation CPUs.
Execute full-custom analog and mixed-signal layout for key blocks from schematics to manufacturable designs. Develop optimized floorplans, placement, and routing while ensuring compliance with performance, power, and reliability targets.
Analyze and optimize CPU cluster performance by evaluating cache hierarchies, interconnects, and memory access behavior. Build and utilize performance models and simulation environments to identify bottlenecks and influence architectural design decisions.
You will collaborate with sales teams and enterprise customers to drive the adoption of AI software and hardware solutions. This involves conducting technical workshops, presentations, and meetings to provide effective solutions and gather feedback for product development.
You will collaborate with sales teams and enterprise customers to drive the adoption of AI software and hardware solutions. This involves providing technical expertise, conducting workshops, and gathering customer feedback to influence product development.
You will develop verification strategies, build robust test environments, and uncover corner cases for high-performance RISC-V CPU cores. The role involves collaborating with architects and designers to own verification efforts from test planning to debugging and issue closure.
The Manufacturing Engineer will own the interface between package design, semiconductor assembly, and final product integration to ensure manufacturability. They are responsible for leading factory commissioning, process transfers, and driving technical issue resolution across the global manufacturing ecosystem.
You will verify the fetch unit for high-performance RISC-V CPU cores by developing verification strategies and creating sophisticated tests. You will collaborate with architects and RTL designers to debug complex failures and ensure correct behavior across various workloads.
Define and own the scalable CPU physical design methodology, including synthesis, floorplanning, and signoff infrastructure. Drive automation, quality metrics, and AI/ML-enabled workflows to improve predictability and PPA outcomes across advanced process nodes.
The Field Application Engineer will serve as the technical bridge between Tenstorrent and customers in Southeast Asia, guiding technical evaluations and deployments. They will troubleshoot hardware and software issues while building strong relationships with regional partners and stakeholders.
You will build and maintain strategic customer relationships while identifying new business opportunities across the APAC region. You will also partner with cross-functional teams to execute regional business strategies and communicate the value of Tenstorrent's AI and compute solutions.
The Director of Finance Systems will lead the strategy, architecture, and implementation of integrated financial technology ecosystems to support company growth. They will partner with cross-functional teams to automate workflows, leverage AI, and ensure scalable financial operations.
Drive the architecture and micro-architecture of compute execution units and subsystems for high-performance RISC-V CPUs. Collaborate with cross-functional teams to translate HPC and AI workload requirements into scalable, efficient hardware designs.
You will own the full enterprise sales lifecycle, from discovery to negotiation and closing, while aligning technical and business needs with AI solutions. You will also collaborate with product, engineering, and marketing teams to develop repeatable sales strategies and drive revenue growth.
Define the market positioning and messaging for Tenstorrent's AI hardware and software stack across various industries. Collaborate with product, engineering, and sales teams to create technical collateral and align the product roadmap with customer needs.
Define the market positioning and messaging for Tenstorrent's AI hardware and software stack across various industries. Develop vertical-specific value propositions and technical collateral while aligning roadmaps with product, engineering, and sales teams.
Implement and verify DFT strategies for high-speed CPU core designs and multi-chiplet System-in-Package programs. Collaborate with RTL, physical design, and verification teams to ensure testability and automate DFT flows using industry-standard EDA tools.
Collaborate with sales teams and enterprise customers to drive the adoption of AI products and solutions. Provide technical guidance through meetings and workshops while feeding customer insights back to product teams to shape the roadmap.
The engineer will build the infrastructure necessary for exploring, testing, and validating chiplet-based systems across hardware, software, and architectural layers. This involves creating a scalable, high-performance emulation ecosystem to support debug, software development, and power/performance analysis for SiP based AI/ML engines.
The role involves architecting and specifying one or more chiplets intended for robotics and automotive applications, translating high-level requirements into detailed architectural direction. This includes identifying impactful features that enhance Power, Performance, Area (PPA), safety, and reliability while collaborating across design, verification, and software teams.
The role involves defining the test strategy for multi-chiplet packages from initial silicon through high volume production, coordinating test, yield, and quality efforts across multiple teams and companies. Responsibilities also include feeding lessons learned back into next-generation SiP architectures, DFT strategy, and test content.
The engineer will lead the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII, focusing on closing high-speed D2D interfaces for multi-die/chiplet architectures. This includes owning the full PD flow, driving timing and verification sign-off, and improving physical design methodologies.
The designer will help define and build next-generation CPU networking architecture for both datacenter and emerging robotics/automotive applications, contributing to current datacenter networking efforts while seeding future low-power robotics/automotive devices. This involves working at the intersection of NoC, performance modeling, and RTL design to guide architectural decisions for AI/ML compute and sensor ingest.
This role is responsible for integrating and optimizing the Low-Level Kernel (LLK) infrastructure for CPU execution while leading the bring-up of a RISC-V-native agentic AI software stack. The lead will collaborate closely with architects, microarchitecture teams, compiler engineers, and AI kernel developers to ensure tight alignment between software capabilities and RISC-V architectural features.
