Develop and execute verification test plans using SystemVerilog and UVM for IPs and SoC components. Debug simulation failures and collaborate with design teams to ensure high-quality silicon delivery for AI, HPC, and Networking applications.
TYLsemi
18 Remote Job Openings at TYLsemi
Design and deliver high-performance analog and mixed-signal circuits, specifically focusing on voltage regulators and power management. Lead collaboration with packaging and SIPI/PI teams to optimize power delivery and ensure first-time-right silicon outcomes.
The role involves end-to-end administration of Microsoft 365, Rippling, and JIRA to ensure seamless integration of collaboration, identity, and HRIS systems. Key duties include managing user lifecycles, optimizing workflows, and implementing security and compliance policies.
Develop and execute mixed-signal verification plans for high-current IVR designs using behavioral modeling and co-simulation. Collaborate with cross-functional teams to debug issues and correlate simulation results with post-silicon validation.
Lead the definition and execution of scalable verification strategies for next-generation SoCs in AI, HPC, and Networking. Develop reusable verification platforms and leverage AI/ML techniques to automate testbench generation and improve coverage closure.
Architect and implement digital PID control loops for high-frequency multi-phase integrated voltage regulators. Translate validated MATLAB/Simulink models into production-quality RTL and perform mixed-signal verification and silicon bring-up.
Own signal and power integrity, as well as package and PDN co-design across chip, package, and board interfaces. Drive SI/PI methodology from early planning through signoff to ensure robust high-speed links and stable power delivery.
Lead the definition and execution of scalable verification strategies for next-generation SoCs in AI, HPC, and Networking. Develop reusable verification platforms and leverage AI/ML techniques to automate testbench generation and improve coverage closure.
Support and operate compute, network, and EDA environments for complex SoC design across digital and analog domains. Maintain AI/ML platforms and automate routine infrastructure tasks using Python and Bash scripts.
Design and implement high-performance RTL for complex SoC components and subsystems targeting AI, HPC, and Networking. Own the micro-architecture definition and integrate high-speed IO protocols while ensuring timing and power efficiency.
Define and drive the end-to-end architecture of next-generation XPUs for AI infrastructure, focusing on scalability and performance. This includes designing compute, memory, and IO subsystems while collaborating with design and DV teams for implementation.
Lead the end-to-end architecture of Integrated Voltage Regulators (IVR), overseeing power conversion topology, digital control, and analog subsystems. Coordinate with engineering teams and foundry partners to drive execution from definition through tape-out for AI compute platforms.
Own the end-to-end development of high-performance analog and mixed-signal blocks from requirements and architecture to simulation and signoff. Collaborate with cross-functional teams to support silicon bring-up, debug, and the implementation of design fixes.
The HSIO Architect defines and owns the high-speed interface architecture for PCIe, UCIe, and Ethernet subsystems across product families. This includes managing signal integrity budgets, guiding PHY selection, and serving as the technical interface for IP vendors and hyperscale customers.
The PMIC Architect owns the end-to-end IVR architecture, including power conversion topology, digital control, and analog subsystems. They are responsible for defining specifications, validating tradeoffs, and driving execution through tape-out while engaging with foundry partners and customers.
Own the high-speed interface architecture across product families, focusing on SerDes and UCIe die-to-die integration. Define signal integrity budgets and serve as the primary technical interface for IP vendors and hyperscaler customers.
Build and manage end-to-end compute, storage, and network infrastructure specifically for EDA and SoC design environments. This includes optimizing EDA license utilization, managing hybrid cloud strategies, and enabling AI/ML infrastructure for engineering workflows.
Lead customer and ecosystem development for SoC products by identifying target accounts in the AI infrastructure market and managing relationships with IP partners and foundries. Translate customer platform requirements into actionable product specifications for R&D and drive participation in industry standards bodies.
