The Principal PCIe Subsystem RTL Lead will own the microarchitecture and integration of PCIe subsystems for high-performance chiplet-based SoCs. This role involves leading RTL design, defining performance budgets, and collaborating with cross-functional teams for silicon bring-up and verification.
Design, implement, and maintain Zephyr RTOS firmware and system software for platform management controllers and application processors. Perform post-silicon bring-up, debug PCIe links, and manage DMA and memory-management interfaces.
Define and lead the architecture and design of next-generation Ethernet Scale-Up Networking solutions for AI and HPC systems. Drive the full development lifecycle from RTL and verification through to silicon bring-up and production.
Lead full-chip or block-level physical design implementation from floorplanning to GDS signoff. Collaborate with cross-functional teams to resolve implementation challenges and ensure high-quality tape-outs.
Define and drive the overall verification architecture for large-scale SoCs while leading the development of reusable, modular, and portable verification platforms. Collaborate with cross-functional teams to implement AI-driven methodologies and ensure first-pass silicon success through rigorous quality metrics.
The role involves owning the micro-architecture and design of SoC infrastructure, including reset sequencing, power management, and secure boot. You will collaborate with cross-functional teams to define hardware/software interfaces and drive power intent sign-off for high-performance AI and HPC applications.
You will own the development and implementation of DFT architecture, including scan insertion, compression, and hierarchical DFT for advanced SoC designs. Additionally, you will collaborate with cross-functional teams to perform ATPG pattern generation, timing closure, and post-silicon debug.
Lead end-to-end physical design implementation from floorplanning to GDSII signoff for complex SOCs. Drive strategies for PPA optimization and mentor junior engineers while collaborating with cross-functional teams.
Lead end-to-end static timing analysis and signoff activities for complex ASIC/SOC designs. Drive timing closure across various scenarios and collaborate with cross-functional teams to ensure successful tape-outs at advanced technology nodes.
Develop and execute mixed-signal verification plans for high-current IVR designs using behavioral modeling and co-simulation. Collaborate with cross-functional teams to debug issues and correlate simulation results with post-silicon lab measurements.
Lead the DFT strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. Collaborate with cross-functional teams to ensure high test coverage, quality, and successful silicon bring-up.
Design and implement high-performance RTL for complex SoC components and subsystems targeting AI, HPC, and Networking. Own the micro-architecture definition and integrate high-speed IO protocols while ensuring timing and power efficiency.
Lead customer and ecosystem development for SoC products by identifying target accounts in the AI infrastructure market and managing relationships with IP partners and foundries. Translate customer platform requirements into actionable product specifications for R&D and drive participation in industry standards bodies.
