You will own the development and implementation of DFT architecture, including scan insertion, compression, and hierarchical DFT for advanced SoC designs. Additionally, you will collaborate with cross-functional teams to perform ATPG pattern generation, timing closure, and post-silicon debug.
TYLsemi
28 Remote Job Openings at TYLsemi
Lead the physical design execution, layout strategy, and integration for analog and mixed-signal IP blocks on advanced FinFET nodes. Manage technical interfaces with external partners and foundry teams while mentoring junior engineers and defining layout methodologies.
You will own the end-to-end IVR architecture, including power conversion topology, digital control engines, and analog subsystems. You will also drive execution from architecture definition through tape-out while engaging with foundry partners and customers.
Develop and maintain complete SoC virtual platforms using Synopsys Virtualizer to enable early architecture validation and software development. Collaborate with cross-functional teams to integrate RTL, SystemC/TLM models, and firmware to improve first-pass silicon success.
Define and drive the end-to-end architecture of next-generation XPUs for AI infrastructure, focusing on scalability and performance. This includes designing compute, memory, and IO subsystems while collaborating with design and software teams to align with real-world workloads.
Develop high-performance RTL designs and SoC components for AI, HPC, and Networking applications using Verilog and System Verilog. Collaborate with cross-functional teams to optimize timing, power, and area while supporting the full ASIC development lifecycle.
Lead the implementation of complex digital SoCs from synthesis through tapeout, focusing on floorplanning, routing, and timing closure. Collaborate with cross-functional teams to ensure physical constraints align with design intent and mentor junior engineers.
Lead end-to-end physical implementation from floorplanning to GDS signoff for advanced semiconductor designs. Collaborate cross-functionally to optimize PPA and mentor junior engineers on design methodologies.
Lead end-to-end physical design implementation from floorplanning to GDSII signoff for complex SOCs. Drive strategies for PPA optimization and mentor junior engineers while collaborating with cross-functional teams.
Lead block-level and full-chip static timing analysis and signoff activities for complex SoC designs. Drive timing closure across multiple modes and corners while collaborating with cross-functional teams to optimize performance, power, and area.
The role involves driving timing closure and signoff activities for complex SoC designs across advanced technology nodes. Responsibilities include performing block-level and full-chip STA, managing timing constraints, and collaborating with cross-functional teams to ensure successful tapeout delivery.
Perform block-level and full-chip IR drop and electromigration analysis for advanced-node SoC designs. Collaborate with cross-functional teams to optimize power delivery networks and ensure clean signoff for tapeout.
Lead end-to-end static timing analysis and signoff activities for complex ASIC/SOC designs. Drive timing closure across various scenarios and collaborate with cross-functional teams to ensure successful tape-outs at advanced technology nodes.
Lead the development and support of advanced VLSI CAD methodologies and automation solutions to improve design productivity and scalability. Architect scalable flows for synthesis, physical design, and signoff while collaborating with cross-functional teams to ensure successful SOC tape-outs.
Develop and execute mixed-signal verification plans for high-current IVR designs using behavioral modeling and co-simulation. Collaborate with cross-functional teams to debug issues and correlate simulation results with post-silicon lab measurements.
The Firmware Architect will lead the end-to-end firmware and embedded software architecture for TYL chiplets, overseeing both on-die and host-side components. They will also drive pre-silicon and post-silicon firmware development and collaborate with cross-functional teams and customers.
Lead the DFT strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. Collaborate with cross-functional teams to ensure high test coverage, quality, and successful silicon bring-up.
Design and deliver high-performance analog and mixed-signal circuits, specifically focusing on voltage regulators and power management. Lead collaboration with packaging and SIPI/PI teams to optimize power delivery and ensure first-time-right silicon outcomes.
The role involves end-to-end administration of Microsoft 365, Rippling, and JIRA to ensure seamless integration of collaboration, identity, and HRIS systems. Key duties include managing user lifecycles, optimizing workflows, and implementing security and compliance policies.
Architect and implement digital PID control loops for high-frequency multi-phase integrated voltage regulators. Translate validated MATLAB/Simulink models into production-quality RTL and perform mixed-signal verification and silicon bring-up.
Lead the definition and execution of scalable verification strategies for next-generation SoCs in AI, HPC, and Networking. Develop reusable verification platforms and leverage AI/ML techniques to automate testbench generation and improve coverage closure.
Design and implement high-performance RTL for complex SoC components and subsystems targeting AI, HPC, and Networking. Own the micro-architecture definition and integrate high-speed IO protocols while ensuring timing and power efficiency.
The HSIO Architect defines and owns the high-speed interface architecture for PCIe, UCIe, and Ethernet subsystems across product families. This includes managing signal integrity budgets, guiding PHY selection, and serving as the technical interface for IP vendors and hyperscale customers.
Define and drive the end-to-end architecture of next-generation XPUs for AI infrastructure, focusing on scalability and performance. This includes designing compute, memory, and IO subsystems while collaborating with design and DV teams for implementation.
Own the end-to-end development of high-performance analog and mixed-signal blocks from requirements and architecture to simulation and signoff. Collaborate with cross-functional teams to support silicon bring-up, debug, and the implementation of design fixes.
Build and manage end-to-end compute, storage, and network infrastructure specifically for EDA and SoC design environments. This includes optimizing EDA license utilization, managing hybrid cloud strategies, and enabling AI/ML infrastructure for engineering workflows.
Own the high-speed interface architecture across product families, focusing on SerDes and UCIe die-to-die integration. Define signal integrity budgets and serve as the primary technical interface for IP vendors and hyperscaler customers.
Lead customer and ecosystem development for SoC products by identifying target accounts in the AI infrastructure market and managing relationships with IP partners and foundries. Translate customer platform requirements into actionable product specifications for R&D and drive participation in industry standards bodies.