Define and lead the architecture and design of next-generation Ethernet Scale-Up Networking solutions for AI and HPC systems. Drive the full development lifecycle from RTL and verification through to silicon bring-up and production.
The role involves developing and maintaining scalable EMIR signoff methodologies for advanced-node SoC designs. You will collaborate with cross-functional teams to drive automation, tool qualification, and robust power integrity closure.
Develop and maintain scalable CAD flows for synthesis, physical design, and signoff while driving automation to enhance design efficiency. Collaborate with cross-functional teams and EDA vendors to resolve infrastructure issues and enable successful tape-outs for complex SOCs.
Define and drive the overall verification architecture for large-scale SoCs while developing reusable and portable verification platforms. Collaborate with cross-functional teams to implement AI-driven methodologies and ensure first-pass silicon success.
Lead the design verification strategy and execution for high-speed interconnect IPs and SoCs. Architect UVM testbenches and drive functional coverage closure while mentoring junior engineers.
The Senior Staff Engineer will lead the verification strategy and execution for high-speed interconnect IPs and SoCs, including the development of scalable UVM testbenches. They will also drive functional coverage closure, perform complex debugging, and mentor junior engineers to ensure high-quality design compliance.
Lead full-chip or block-level physical design implementation from floorplanning to GDS signoff. Collaborate with cross-functional teams to resolve implementation challenges and ensure high-quality tape-outs.
You will own the end-to-end development of analog and mixed-signal blocks, from architecture and transistor-level design to silicon validation. You will also collaborate cross-functionally to ensure system-level success and contribute to design methodology improvements.
Define and drive the overall verification architecture for large-scale SoCs while leading the development of reusable, modular, and portable verification platforms. Collaborate with cross-functional teams to implement AI-driven methodologies and ensure first-pass silicon success through rigorous quality metrics.
The role involves owning the micro-architecture and design of SoC infrastructure, including reset sequencing, power management, and secure boot. You will collaborate with cross-functional teams to define hardware/software interfaces and drive power intent sign-off for high-performance AI and HPC applications.
Develop and execute verification test plans for IPs, subsystems, and SoC components using SystemVerilog and UVM. Collaborate with design and architecture teams to debug simulation failures and ensure high-quality silicon delivery.
You will own the development and implementation of DFT architecture, including scan insertion, compression, and hierarchical DFT for advanced SoC designs. Additionally, you will collaborate with cross-functional teams to perform ATPG pattern generation, timing closure, and post-silicon debug.
You will own the end-to-end IVR architecture, including power conversion topology, digital control engines, and analog subsystems. You will also drive execution from architecture definition through tape-out while engaging with foundry partners and customers.
Develop and maintain complete SoC virtual platforms using Synopsys Virtualizer to enable early architecture validation and software development. Collaborate with cross-functional teams to integrate RTL, SystemC/TLM models, and firmware to improve first-pass silicon success.
Define and drive the end-to-end architecture of next-generation XPUs for AI infrastructure, focusing on scalability and performance. This includes designing compute, memory, and IO subsystems while collaborating with design and software teams to align with real-world workloads.
Develop high-performance RTL designs and SoC components for AI, HPC, and Networking applications using Verilog and System Verilog. Collaborate with cross-functional teams to optimize timing, power, and area while supporting the full ASIC development lifecycle.
Lead end-to-end physical design implementation from floorplanning to GDSII signoff for complex SOCs. Drive strategies for PPA optimization and mentor junior engineers while collaborating with cross-functional teams.
Perform block-level and full-chip IR drop and electromigration analysis for advanced-node SoC designs. Collaborate with cross-functional teams to optimize power delivery networks and ensure clean signoff for tapeout.
Lead end-to-end static timing analysis and signoff activities for complex ASIC/SOC designs. Drive timing closure across various scenarios and collaborate with cross-functional teams to ensure successful tape-outs at advanced technology nodes.
Develop and execute mixed-signal verification plans for high-current IVR designs using behavioral modeling and co-simulation. Collaborate with cross-functional teams to debug issues and correlate simulation results with post-silicon lab measurements.
The Firmware Architect will lead the end-to-end firmware and embedded software architecture for TYL chiplets, overseeing both on-die and host-side components. They will also drive pre-silicon and post-silicon firmware development and collaborate with cross-functional teams and customers.
Lead the DFT strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. Collaborate with cross-functional teams to ensure high test coverage, quality, and successful silicon bring-up.
Architect and implement digital PID control loops for high-frequency multi-phase integrated voltage regulators. Translate validated MATLAB/Simulink models into production-quality RTL and perform mixed-signal verification and silicon bring-up.
Design and deliver high-performance analog and mixed-signal circuits, specifically focusing on voltage regulators and power management. Lead collaboration with packaging and SIPI/PI teams to optimize power delivery and ensure first-time-right silicon outcomes.
Lead the definition and execution of scalable verification strategies for next-generation SoCs in AI, HPC, and Networking. Develop reusable verification platforms and leverage AI/ML techniques to automate testbench generation and improve coverage closure.
Design and implement high-performance RTL for complex SoC components and subsystems targeting AI, HPC, and Networking. Own the micro-architecture definition and integrate high-speed IO protocols while ensuring timing and power efficiency.
Build and manage end-to-end compute, storage, and network infrastructure specifically for EDA and SoC design environments. This includes optimizing EDA license utilization, managing hybrid cloud strategies, and enabling AI/ML infrastructure for engineering workflows.
The HSIO Architect defines and owns the high-speed interface architecture for PCIe, UCIe, and Ethernet subsystems across product families. This includes managing signal integrity budgets, guiding PHY selection, and serving as the technical interface for IP vendors and hyperscale customers.
Define and drive the end-to-end architecture of next-generation XPUs for AI infrastructure, focusing on scalability and performance. This includes designing compute, memory, and IO subsystems while collaborating with design and DV teams for implementation.
Own the high-speed interface architecture across product families, focusing on SerDes and UCIe die-to-die integration. Define signal integrity budgets and serve as the primary technical interface for IP vendors and hyperscaler customers.
Lead customer and ecosystem development for SoC products by identifying target accounts in the AI infrastructure market and managing relationships with IP partners and foundries. Translate customer platform requirements into actionable product specifications for R&D and drive participation in industry standards bodies.
