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AI Summary
Lead the physical design execution, layout strategy, and integration for analog and mixed-signal IP blocks on advanced FinFET nodes. Manage technical interfaces with external partners and foundry teams while mentoring junior engineers and defining layout methodologies.
About the Role
TYLsemi is seeking an experienced Analog / Mixed-Signal Layout Lead to drive physical design execution for analog and mixed-signal IP blocks on advanced FinFET process nodes. This role owns layout strategy, integration, and sign-off for high-performance power and analog circuits, and serves as the primary technical interface with external layout/design-service partners and foundry teams.
What You’ll Do
- Lead layout planning, floorplanning, and execution for analog and mixed-signal blocks (e.g., power converters, IVRs, references, amplifiers, ADC/DAC front-ends) on FinFET-based advanced nodes.
- Define and enforce analog layout techniques: matching, symmetry, common-centroid structures, guard-ringing, shielding, and parasitic-aware placement/routing for sensitive analog nets.
- Own integration guidelines between analog/mixed-signal blocks and digital logic, ensuring clean floorplan partitioning, power delivery, and signal integrity across the top-level chip.
- Identify and resolve advanced-node layout issues — including multi-patterning (MP) constraints, color-aware routing, restrictive design rules (RDRs), via pillars, local interconnect limitations, and device-level layout-dependent effects (LDE, well-proximity, STI stress).
- Drive DRC/LVS/PERC/antenna closure and coordinate ECO layout cycles with design and verification teams.
- Manage layout schedules, milestones, and quality across internal teams and external layout vendors/subcontractors, including scope definition, kickoff, technical reviews, and issue resolution.
- Interface with packaging teams for integration on advanced packaging (2.5D/3D, microbump, RDL) layout requirements.
- Define and drive layout methodology strategy, including use of APR (Automatic Place & Route) tools for applicable analog-assisted and mixed-signal blocks, custom scripting/automation (e.g., SKILL, Python) to speed up placement, routing, and DRC/LVS cleanup, and PCells/parameterized layout generation to improve reuse and reduce turnaround time.
- Mentor junior layout engineers and establish reusable layout methodologies, checklists, and best-practice documentation.
What We’re Looking For
- Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field.
- 10+ years of layout experience in the semiconductor industry, with significant time on FinFET process nodes (16nm and below).
- 2+ years of leadership experience, such as leading a layout team, mentoring engineers, or owning layout schedules/deliverables across a project.
- Strong hands-on expertise in analog/mixed-signal layout techniques for power management, reference, or precision analog circuits.
- Deep familiarity with advanced-node layout constraints: multi-patterning, restricted design rules, device orientation/matching rules, and layout-dependent effects.
- Proven experience defining or applying analog-digital integration guidelines at the block and top level.
- Familiarity with layout automation and APR methodologies, and their applicability/limitations for analog and mixed-signal design.
- Track record of managing or closely collaborating with external layout teams, design service providers, or offshore layout groups.
- Proficiency with industry-standard layout/verification tools (e.g., Cadence Virtuoso, Calibre DRC/LVS/PERC).
- Solid understanding of parasitic extraction, IR drop, EM/reliability considerations for power-carrying layout.
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