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TYLsemi

RTL Design Engineer

Posted 2 months ago
5-10 years experience
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AI Summary

Develop high-performance RTL designs and SoC components for AI, HPC, and Networking applications using Verilog and System Verilog. Collaborate with cross-functional teams to optimize timing, power, and area while supporting the full ASIC development lifecycle.

Role Overview

TylSemi Solutions Private Limited is seeking a talented and motivated RTL Design Engineer to join our growing semiconductor design team. In this role, you will be responsible for the design and development of high-performance digital IPs and SoC components for next-generation AI, HPC, and Networking applications. You will work closely with architecture, verification, physical design, and software teams to deliver robust and scalable silicon solutions.


What You'll Do

  • Develop RTL designs using Verilog/System Verilog based on architectural and microarchitecture specifications.
  • Participate in microarchitecture definition and design reviews.
  • Implement high-performance, area-efficient, and power-optimized digital logic.
  • Develop and maintain design documentation, specifications, and implementation guidelines.
  • Collaborate with verification engineers to define verification strategies and debug functional issues.
  • Perform RTL simulations and support design validation activities.
  • Analyze synthesis results and work with physical design teams to optimize timing, power, and area.
  • Support SoC integration activities and resolve integration-related issues.
  • Participate in design reviews, code reviews, and quality improvement initiatives.
  • Work closely with cross-functional teams throughout the ASIC development lifecycle.

Required Qualifications

  • Bachelor's or master's degree in electrical engineering, Electronics Engineering, Computer Engineering, or related field.
  • 5+years experience in RTL design and digital IC development.
  • Strong understanding of digital design fundamentals, computer architecture, and ASIC design flow.
  • Proficiency in:
    • Verilog/System Verilog
    • RTL design and coding methodologies
    • Logic design and finite state machines (FSMs)
    • Clock domain crossing (CDC) concepts
    • Low-power design fundamentals
  • Experience with simulation and debugging tools.
  • Familiarity with synthesis and timing analysis concepts.
  • Strong analytical and problem-solving skills.

Preferred Qualifications

  • Experience designing IPs or subsystems for AI, HPC, Networking, or data-center applications.
  • Knowledge of industry-standard protocols such as:
    • AXI/AHB/APB
    • PCIe
    • DDR
    • Ethernet
    • CXL
    • UCIe
  • Familiarity with scripting languages such as Python, Perl, Shell, or TCL.
  • Exposure to low-power design methodologies and power intent formats (UPF/CPF).
  • Understanding of linting, CDC, RDC, and formal verification tools.
  • Experience with FPGA prototyping is a plus.

Key Attributes

  • Strong attention to detail and commitment to design quality.
  • Passion for semiconductor innovation and cutting-edge technologies.
  • Excellent debugging and problem-solving abilities.
  • Ability to work effectively in a collaborative and fast-paced environment.
  • Strong communication and teamwork skills.
  • Ownership mindset with a focus on delivering high-quality silicon.

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