Senior Engineer – RV (EM/IR)

Role Overview 

We are looking for a highly motivated Senior Engineer – EM/IR to join the Physical Design and Signoff team. In this role, you will be responsible for performing power integrity analysis including IR drop and electromigration (EM) checks for advanced-node SoC designs. You will work closely with Physical Design, Power, and Package teams to ensure robust power delivery network implementation and reliable signoff closure. The ideal candidate should have strong fundamentals in power integrity analysis, signoff methodologies, and advanced-node implementation challenges. 

What You’ll Do 

• Perform block-level and full-chip IR drop and electromigration (EM) analysis for advanced-node designs 

• Analyze and debug static and dynamic IR violations to achieve power integrity signoff closure 

• Collaborate with Physical Design, Floorplanning, CTS, Routing, and Package teams to optimize power delivery networks 

• Run and interpret power integrity analysis across multiple operating conditions and scenarios 

• Support EM analysis by evaluating current density, reliability limits, and thermal impacts 

• Develop and improve IR/EM automation flows, scripts, and signoff methodologies 

• Support tapeout activities and ensure clean IR/EM signoff delivery 

What We’re Looking For 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline 

• 5+ years of experience in EM/IR analysis, power integrity, or Physical Design signoff roles 

• Strong understanding of static and dynamic IR drop analysis, electromigration concepts, and power grid optimization 

• Hands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent 

• Good understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction 

• Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement 

Good to Have 

• Experience with advanced technology nodes such as 7nm, 5nm, or below 

• Exposure to package-aware analysis, thermal analysis, and low-power methodologies 

• Understanding of power-aware signoff methodologies and reliability verification flows 

Success in This Role Looks Like 

• Achieving clean IR/EM signoff with robust power integrity across all operating conditions 

• Efficient identification and resolution of power integrity and reliability issues 

• Improved productivity through automation and methodology enhancements 

• Successful collaboration across cross-functional teams leading to timely tapeout execution 

Location 

Hybrid / On-site – Bengaluru / Remote - India