Principal Physical Design Engineer

Role Overview 

We are seeking a highly experienced Principal Physical Design Engineer to lead complex ASIC/SOC physical implementation activities across advanced technology nodes. The role requires deep expertise in full-chip and block-level implementation, technical leadership in achieving best-in-class PPA (Power, Performance, Area), and ownership of high-quality tape-outs. The ideal candidate will collaborate closely with cross-functional teams and drive methodology improvements, design closure strategies, and mentoring initiatives. ¹ 

What You’ll Do 

• Lead end-to-end physical design implementation from floorplanning through GDSII signoff for complex SOCs and subsystems. 

• Define and drive implementation strategies for timing, congestion, power, area, IR/EM, and signal integrity closure. 

• Collaborate with RTL, STA, DFT, Packaging, and CAD teams to resolve complex design and integration challenges. 

• Own physical signoff including timing, DRC, LVS, IR drop, EM, and reliability analysis. 

• Drive advanced node implementation methodologies and optimize design QoR across multiple projects. 

• Develop and improve automation scripts, flows, and reusable methodologies for implementation efficiency. 

• Lead technical reviews, mentor junior engineers, and provide project execution guidance. 

• Support tape-out activities and customer/escalation debugging when required. 

What We’re Looking For 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 

• 12+ years of hands-on experience in ASIC/SOC physical design implementation. 

• Strong expertise in floorplanning, placement, CTS, routing, timing closure, and physical verification. 

• Hands-on experience with EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, StarRC, and Voltus/RedHawk. 

• Deep understanding of advanced node challenges including low-power design, SI, IR/EM, and variability analysis. 

• Proven experience delivering successful tape-outs at advanced technology nodes (7nm/5nm/3nm preferred). 

• Strong scripting and automation skills using Tcl, Python, Perl, or Shell. 

• Excellent problem-solving, leadership, communication, and stakeholder management skills. 

Good to Have 

• Experience with hierarchical SOC integration and top-level implementation. 

• Exposure to 3D IC, chiplet, or package-aware implementation methodologies. 

• Experience in AI/ML-driven EDA optimization techniques. 

Success in This Role Looks Like 

• Successful delivery of complex SOC designs meeting aggressive PPA and schedule targets. 

• Consistent achievement of implementation and signoff closure with high-quality tape-outs. 

• Improved team productivity through methodology enhancements and automation. 

• Strong technical leadership, mentoring impact, and cross-functional collaboration.