Virtual Platform Development Lead

Role Overview

We are seeking an experienced Virtual Platform Development Lead to develop and own the virtual platform for next-generation SoCs targeting AI, HPC, and Networking applications. This role will leverage existing Virtualizer Platform tools to enable early architecture validation, hardware/software co-development, firmware development, and software bring-up well before silicon availability.

The ideal candidate will have hands-on experience building complete SoC virtual platforms using a combination of RTL and SystemC/TLM models, and will work closely with architecture, design, verification, and firmware teams to accelerate product development and improve first-pass silicon success.

What You’ll Do  

• Develop and maintain complete SoC virtual platforms using Virtualizer Platform
• Integrate SoCs using a combination of RTL, SystemC/TLM models, processor models, memory models, and peripheral models.
• Develop validation scenarios to verify architectural correctness, boot flows, data movement, and key system use cases.
• Enable early firmware and software development before RTL and silicon availability.
• Debug complex issues spanning architecture, RTL, SystemC models, firmware, and software.
• Collaborate with Architecture, RTL, Design Verification, and Firmware teams to validate architectural intent and improve overall system quality.
• Develop reusable methodologies, automation, and best practices for virtual platform development.

What We’re Looking For 

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8+ years of semiconductor design experience.
• Strong hands-on experience with Synopsys Virtualizer.
• Experience integrating complete SoCs using RTL and SystemC/TLM models.
• Strong knowledge of C/C++, SystemC, and transaction-level modeling.
• Good understanding of SoC architecture and hardware/software co-design.
• Experience with high-speed interfaces such as PCIe, UCIe, and Ethernet. Knowledge of DDR/HBM memory interfaces is a plus.

Key Attributes

• Strong system-level thinking and debugging skills.
• Passion for building scalable and reusable virtual platforms.
• High ownership with a focus on quality and first-pass silicon success.
• Excellent collaboration across architecture, design, verification, firmware, and software teams.

Success Metrics

Early availability of virtual platforms for architecture validation and software development.

High-quality, reusable virtual platform infrastructure across multiple SoC programs.

Faster firmware and software readiness with reduced integration issues.

Improved first-pass silicon success through early system validation.