The engineer will own the end-to-end FPGA development process, including microarchitecture, RTL design, and lab-based silicon validation. They will also collaborate with cross-functional teams to build prototypes and optimize system performance for AI inference platforms.
You will own the identity and access management, cloud infrastructure, and developer tooling while leading the migration to a secure hybrid-cloud environment. Additionally, you will be responsible for defining security foundations, including threat detection, incident response, and infrastructure as code.
The Senior Mechanical Engineer will own the mechanical, thermal-mechanical, and enclosure design for AI inference platforms from concept through volume production. They will serve as the primary interface for contract manufacturers and lead DFM/DFA reviews to ensure design robustness and cost-effectiveness.
The Senior Recruiter will own the full-cycle recruiting process for hardware engineering roles, partnering with leaders to define hiring priorities and candidate profiles. They will also build pipelines of passive candidates and utilize AI tools to improve recruiting operations and candidate engagement.
Lead and grow an engineering team responsible for production platforms, fleet orchestration, and reliability. Establish technical roadmaps and operational standards to ensure scalable, high-availability production systems.
Lead and grow an engineering team responsible for the serving layer, including API fidelity, tokenization, tool calling, and model integration. Establish technical roadmaps and ensure high-performance, reliable production operations for LLM serving systems.
Define the multi-generation platform software architecture for AI inference silicon and ensure seamless integration across firmware, operating systems, and runtime. Lead architecture reviews, drive cross-team technical decisions, and provide reference implementations for critical interfaces.
You will lead the microarchitecture and RTL design for complex IP blocks and subsystems, ensuring high-performance silicon outcomes. You will also mentor junior engineers and collaborate across cross-functional teams to drive architectural tradeoffs and signoff processes.
You will design, implement, and verify IP blocks and subsystems for inference ASICs using SystemVerilog RTL. You will also collaborate with cross-functional teams to resolve design issues, track PPA metrics, and contribute to microarchitecture documentation.
The engineer will own synthesis, timing convergence, and implementation readiness for key partitions within an AI accelerator roadmap. They will collaborate with cross-functional teams to develop synthesis flows, optimize netlists, and drive physical-aware optimization.
You will own the end-to-end DFT implementation for AI accelerators, from micro-architecture definition to silicon bring-up. This involves integrating DFT IP, driving pre-silicon verification, and collaborating with physical design and cross-functional teams to ensure high-quality silicon.
Develop and maintain simulation infrastructure, including analytical performance models and functional simulators for inference systems. Collaborate with hardware and software teams to validate architectural assumptions and ensure simulator consistency with production environments.
The engineer will contribute to the physical implementation of AI accelerators from floorplanning through tapeout. They will drive implementation methodology, timing closure, and cross-functional collaboration to achieve world-class PPA.
The engineer will embed with sub-teams to build and deploy agentic workflows that improve developer productivity across firmware, runtime, and simulation. They will also own the shared skills repository and internal agent tooling to ensure high-quality, evaluated automation within the engineering lifecycle.
The role involves defining the silicon and systems product line, from accelerator architecture to rack-scale inference systems. You will translate market signals into engineering requirements and manage the product roadmap in collaboration with engineering and go-to-market teams.
The Technical Product Manager will own the end-to-end planning of the AI inference software stack, translating model advancements into actionable engineering requirements. They will serve as the primary bridge between engineering, go-to-market teams, and ecosystem partners to ensure a competitive and well-documented product roadmap.
The Senior Recruiter will own full-cycle recruiting for software and systems engineering roles, managing the entire process from intake to offer. They will also partner with engineering leaders to develop effective sourcing strategies and build strong candidate pipelines in a competitive market.
Own the power architecture, estimation, and optimization for AI accelerators across the full development lifecycle. Collaborate cross-functionally to ensure industry-leading performance-per-watt and meet aggressive thermal constraints.
Own the hardware security architecture for an AI accelerator platform, focusing on protecting customer models, data, and firmware. This includes defining silicon security, implementing secure boot, and partnering cross-functionally to embed security throughout the product lifecycle.
Own the end-to-end physical implementation of AI accelerators from floorplanning through tapeout. Lead implementation methodology and partner with cross-functional teams to achieve world-class PPA and signoff-quality results.
Define the architecture for next-generation AI inference accelerators, focusing on transformer models and high-performance silicon implementation. Collaborate across software and hardware teams to develop performance models, specifications, and a long-term product roadmap.
Own the synthesis methodology and timing convergence to transform RTL into implementation-ready netlists for AI accelerators. Act as the technical bridge between architecture, RTL, and physical implementation teams while managing external vendor quality.
Own the end-to-end DFT and DFx strategy for AI inference accelerators, from architecture definition to silicon bring-up. Lead the implementation of scan, BIST, and ATPG strategies while managing external design partners and cross-functional teams.
Lead the end-to-end emulation strategy on the Cadence Palladium platform for next-generation AI inference ASICs. Collaborate across RTL, DV, and Software teams to build virtual environments that accelerate firmware and OS bring-up.
You will lead the microarchitecture and RTL design of complex IP blocks and subsystems for inference ASICs. You will also mentor junior engineers and collaborate across teams to ensure successful silicon signoff and performance targets.
