The Technical Product Manager will own the end-to-end planning of the AI inference software stack, translating model advancements into actionable engineering requirements. They will serve as the primary bridge between engineering, go-to-market teams, and ecosystem partners to ensure a competitive and well-documented product roadmap.
The role involves defining the silicon and systems product line, from accelerator architecture to rack-scale inference systems. You will translate market signals into engineering requirements and manage the product roadmap in collaboration with engineering and go-to-market teams.
The Senior Recruiter will own full-cycle recruiting for software and systems engineering roles, managing the entire process from intake to offer. They will also partner with engineering leaders to develop effective sourcing strategies and build strong candidate pipelines in a competitive market.
Own the power architecture, estimation, and optimization for AI accelerators across the full development lifecycle. Collaborate cross-functionally to ensure industry-leading performance-per-watt and meet aggressive thermal constraints.
Own the end-to-end physical implementation of AI accelerators from floorplanning through tapeout. Lead implementation methodology and partner with cross-functional teams to achieve world-class PPA and signoff-quality results.
Own the hardware security architecture for an AI accelerator platform, focusing on protecting customer models, data, and firmware. This includes defining silicon security, implementing secure boot, and partnering cross-functionally to embed security throughout the product lifecycle.
Define the architecture for next-generation AI inference accelerators, focusing on transformer models and high-performance silicon implementation. Collaborate across software and hardware teams to develop performance models, specifications, and a long-term product roadmap.
Own the synthesis methodology and timing convergence to transform RTL into implementation-ready netlists for AI accelerators. Act as the technical bridge between architecture, RTL, and physical implementation teams while managing external vendor quality.
Own the end-to-end DFT and DFx strategy for AI inference accelerators, from architecture definition to silicon bring-up. Lead the implementation of scan, BIST, and ATPG strategies while managing external design partners and cross-functional teams.
Lead the end-to-end emulation strategy on the Cadence Palladium platform for next-generation AI inference ASICs. Collaborate across RTL, DV, and Software teams to build virtual environments that accelerate firmware and OS bring-up.
You will lead the microarchitecture and RTL design of complex IP blocks and subsystems for inference ASICs. You will also mentor junior engineers and collaborate across teams to ensure successful silicon signoff and performance targets.
You will develop and execute advanced verification strategies for AI inference ASICs while collaborating with design and architecture teams to ensure functional coverage. The role involves leading verification environments, managing testbenches, and driving debugging efforts for both pre-silicon and post-silicon validation.
The role involves managing integrated program plans for customer deployments and ASIC software releases across the full silicon lifecycle. You will coordinate cross-functional dependencies between hardware and software teams to ensure aligned delivery and milestone achievement.
The Lead Emulation Engineer will define and execute the end-to-end emulation strategy for the next-generation AI Inference ASIC, overseeing the Palladium Z3 cluster management and synchronization between design and software teams. This role involves leading the creation of test environments, developing comprehensive test plans, and leading deep-dive debugging sessions for complex SoC-level issues.
