You will develop and maintain a low-level ML model execution framework in Rust while optimizing model performance for custom hardware. Additionally, you will be responsible for porting, debugging, and productizing various generative AI models.
You will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. This includes authoring specifications, architecting complex RTL designs, and collaborating with cross-functional teams to resolve implementation and timing issues.
Lead the definition and technology roadmap for next-generation AI inference compute products across silicon, hardware, and software. Engage with customers, partners, and internal stakeholders to drive product strategy, competitive analysis, and successful project execution.
You will be responsible for the microarchitecture and design implementation of a high-performance convolutional neural network accelerator ASIC. This includes authoring specifications, RTL implementation, IP integration, and collaborating with verification and physical design teams.
Lead the architectural planning and design of next-generation AI processors for generative AI inference acceleration. Oversee the full ASIC development lifecycle, from technical specifications and modeling to collaborating with cross-functional engineering teams.
Lead all phases of ASIC verification to ensure the pre-silicon correctness of next-generation processors for generative AI inference. This includes developing test strategies, implementing verification environments using SystemVerilog and UVM, and mentoring other verification engineers.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and the full product cycle from lab bringup to shipping.
Lead all phases of ASIC verification to ensure the pre-silicon correctness of next-generation processors for generative AI inference acceleration. Develop comprehensive test strategies, verification environments, and scripts while mentoring other verification engineers.
Lead the management of EDA tool flows and engineering workflow development for multimodal generative AI inference acceleration products. Drive the optimization and implementation of new EDA tools and technologies across the full ASIC chip design process.
Responsible for the Design Verification Testing (DVT) and sustaining of next-generation hardware products for generative AI inference acceleration. This includes driving hardware bring-up, debugging issues, and ensuring systems meet performance and reliability specifications.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and product certification processes.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and the full product cycle from lab bringup to shipping.
