You will develop and optimize low-level kernels for LLM inference while building benchmarking and profiling tools to analyze hardware performance. You will collaborate with engineering teams to translate performance insights into practical improvements for generative AI systems.
You will develop agentic workflows to optimize LLM inference performance on custom silicon and collaborate with hardware architects to refine numerical formats. Your role involves taking new model architectures from reference code to performant execution while ensuring numerical quality and scalability.
You will lead the design and development of system-level services, tools, and platform software for AI inference systems. This involves close collaboration with hardware and silicon teams on firmware, bootloaders, and performance optimization.
The working student will conduct experiments on LLM quantization to optimize inference performance and model quality. They will build reusable evaluation tooling and collaborate with engineers to analyze latency, throughput, and memory usage on custom hardware.
You will design and develop distributed cloud services using Rust while maintaining in-house software and building APIs for generative AI. Additionally, you will collaborate across teams to define design specifications and orchestrate agent teams to implement new features.
You will be responsible for enhancing and maintaining the internal developer platform, including CI pipelines, ML workflow orchestration, and developer environments. Additionally, you will manage GCP cloud infrastructure and develop internal developer-centric services using Rust.
You will lead ASIC front-end physical design and engineering workflow development for multimodal generative AI inference acceleration products. You will also guide colleagues in improving physical design aspects at both the block and full-chip levels within an agile HPC environment.
You will lead ASIC physical STA design and workflow development for multimodal generative AI inference acceleration products. This role involves driving optimization, implementation, and timing exploration workflows while collaborating with the ASIC team on full-chip timing closure.
You will implement new architecture features and algorithms in the inference accelerator model while validating them against architecture specifications and RTL. Additionally, you will write test infrastructure, maintain the codebase, and collaborate with hardware and software teams to resolve discrepancies.
Manage end-to-end full-cycle recruiting across technical and business functions including ASIC, hardware, and software engineering. Partner with hiring managers to define requirements, build sourcing strategies, and deliver high-quality hires in a competitive market.
You will build and extend simulation-based performance models to predict how generative AI inference workloads perform across various system scales. Additionally, you will collaborate with cross-functional teams to validate these models against real hardware and provide analytical insights for architectural decisions.
You will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. This includes authoring specifications, architecting complex RTL designs, and collaborating with cross-functional teams to resolve implementation and timing issues.
Lead the definition and technology roadmap for next-generation AI inference compute products across silicon, hardware, and software. Engage with customers, partners, and internal stakeholders to drive product strategy, competitive analysis, and successful project execution.
You will be responsible for the microarchitecture and design implementation of a high-performance convolutional neural network accelerator ASIC. This includes authoring specifications, RTL implementation, IP integration, and collaborating with verification and physical design teams.
Lead the architectural planning and design of next-generation AI processors for generative AI inference acceleration. Oversee the full ASIC development lifecycle, from technical specifications and modeling to collaborating with cross-functional engineering teams.
Lead all phases of ASIC verification to ensure the pre-silicon correctness of next-generation processors for generative AI inference. This includes developing test strategies, implementing verification environments using SystemVerilog and UVM, and mentoring other verification engineers.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and the full product cycle from lab bringup to shipping.
Lead all phases of ASIC verification to ensure the pre-silicon correctness of next-generation processors for generative AI inference acceleration. Develop comprehensive test strategies, verification environments, and scripts while mentoring other verification engineers.
Responsible for the Design Verification Testing (DVT) and sustaining of next-generation hardware products for generative AI inference acceleration. This includes driving hardware bring-up, debugging issues, and ensuring systems meet performance and reliability specifications.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and product certification processes.
Own the hardware system engineering for AI products, including schematic capture, PCB design, and mechanical integration. Collaborate with cross-functional teams to manage component selection, vendor qualification, and the full product cycle from lab bringup to shipping.
