Sr. Engineer, Layout Design

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

The Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. The Sr. Layout Design Engineer will review, and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality. It is not necessary to meet all job requirements to be a qualified candidate for the position. 

Responsibilities:

• Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones
• Lead Top-level chip-planning and perform functional-block-level, block-level, sub-block level, leaf cell, standard cell custom layouts for CMOS and BiCMOScircuits
• Perform schematic-driven layout and design constraints
• Design die-area efficient layouts according to circuit designer requirements
• Perform block or top-level layout designs
• Perform floor-planning, power line planning, shielding, and device-matching layout
• Verify layouts. Pass DRC, LVS, and ERC
• Contribute to various chip-level routing and layout needs
• Perform chip level integration, verifications, and tape-out
• Support other projects as needed by management
• Train junior layout engineers and offshore layout contractors
• Contribute to developing common best practices and workflow across all sites
• Contribute to build process and procedures to achieve high layout quality

Qualifications & Requirements:

Desired Characteristics & Attributes: 

Compensation: 

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. 

• Innovation on Top – Philosophies of Innovation with Rajesh Vashist
• Fabrication Knowledge – An Interview with Rajesh Vashist
• SiTime Corporation – YouTube