Custom Layout Engineer (Principal/Lead)

 Posted 2 months ago
     
10+ years experience
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AI Summary

The role involves leading top-level layout activities for analog, mixed-signal, and AMS blocks on advanced nodes down to 2nm, ensuring high quality and manufacturability. Responsibilities include performing and supporting all necessary physical verifications and developing scripts to enhance layout productivity.
THE COMPANY
Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn). 
 
THE ROLE
We are seeking a highly skilled Custom Layout Engineer (Principal/Lead) to play a key role in delivering high-quality analog and mixed-signal IP for our chiplet-based solutions. You will take ownership of layout execution from early planning through tape-out, working closely with analog designers to ensure performance, robustness, and manufacturability across advanced technology nodes.This role is well suited to engineers who enjoy deep, hands-on technical ownership and working closely with design teams in a fast-moving, high-impact environment.
Hiring Manager: Christian Borelli, Founder and CSO. 
 
KEY RESPONSIBILITIES
  • Analog & AMS Layout Ownership: Lead Top Level layout activities for analog, mixed-signal, and AMS blocks and macros, ensuring high-quality, robust, and manufacturable implementations.
  • Advanced Node Layout: able to work on the most advanced technology nodes down to 2nm, ensuring performance and reliability at advanced nodes.
  • Verification & Sign-off: Perform and support DRC, LVS, extraction, EMIR, ESD/LUP, and PERC verification, addressing issues efficiently and thoroughly.
  • Collaboration with Design Teams: Work closely with analog and mixed-signal designers to understand circuit intent, constraints, and trade-offs, translating them into optimal physical implementations.
  • Scripting & Automation: Develop and maintain scripts (e.g. Skill/TCL) to improve layout productivity, consistency, and quality.
  • Mentorship & Technical Leadership: Technically leading a team of layout engineers across projects and customers.
 
WHAT WE’RE LOOKING FOR
Must-have Technical skills:
  • Bachelor’s degree in Electrical Engineering or related field
  • 10–15+ years of experience in analog IC layout
  • Strong understanding of analog layout concepts, parasitics, and high-frequency design techniques
  • Proven experience delivering blocks and macros to successful, high-quality tape-out
  • Hands-on experience with FinFET technologies (e.g. 5/4 nm) at TSMC/SAMSUNG
  • Hands-on experience with GAAFET technologies (2nm or below) at TSMC/SAMSUNG
  • Exposure to multiple foundries (e.g. TSMC, Samsung, GlobalFoundries)
  • Proficiency with Cadence Virtuoso, Synopsys Custom Compiler, and physical verification tools such as Calibre and ICV
  • Experience with EMIR, ESD/LUP, and PERC verification flows
  • Skill and/or TCL scripting experience
Soft & Professional Skills:
  • Clear, structured communication in professional English—able to explain complex results concisely
  • Customer oriented communication
  • Collaborative and feedback-oriented mindset
  • Demonstrated ability to mentor and guide less experienced engineers
  • Strong ownership, reliability, and follow-through
  • Curious, self-motivated attitude, eager to learn and explore new tools or methods
  • High level of integrity and professionalism in representing the company and handling sensitive information.
 
OUR CULTURE
We’re a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere! 
  • Our values are our north star: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.
  • Connected, even remotely: We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.
  • High ownership, real impact: Everyone contributes directly to customer-facing IP. Your work doesn’t disappear into layers of management – it ships.
  • How we work: We move fast but thoughtfully, communicate openly, and balance autonomy with support. Technical decisions are debated openly and grounded in data, trade-offs, and first-principles thinking.
 
WHY JOIN US
  • Remote-first flexibility – work from anywhere, with flexible hours
  • Equipment & setup – we’ll provide the tools you need to succeed
  • High-impact projects – design real analog IP used in customer silicon
  • Supportive team culture – a dedicated manager and a team of colleagues ready to help
  • Competitive, transparent compensation – adjusted for your location and engagement model
  • Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

RECRUITMENT PROCESS
  1. Founder Call (30 min) – mutual introduction and interest alignment
  2. Technical Interview (60 min)  –  fundamentals, reasoning, and problem-solving
  3. Presentation (45 min) – short presentation on a topic of your choice, to assess clarity, structure, and confidence in presenting your work
  4. HR & Culture Call (45 min)  values, collaboration style, and ways of working
  5. Offer & Next Steps (30 min) – offer walkthrough, alignment on details, and next steps, discussed in a final call with the founder.

If you don’t meet every requirement but feel excited about the role, apply anyway. We value curiosity, integrity, and potential as much as experience.

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