Design and implement digital blocks for PCS and interface IP using Verilog/SystemVerilog while building testbenches for verification. Collaborate with analog and layout engineers to support mixed-signal simulations and contribute to design documentation.
The CTO will define the long-term technology vision for electrical and photonic interconnects while leading the CTO Office and technical leadership team. They are responsible for driving the IP roadmap, ensuring design closure for customer silicon, and acting as the primary technical voice for partners and investors.
Lead the layout execution of analog and mixed-signal IP from planning through tape-out for chiplet-based solutions. Collaborate with designers to ensure high-performance, manufacturable implementations across advanced technology nodes.
