Staff Engineer – PV (Physical Verification)

Role Overview 

We are seeking a highly skilled Staff Engineer – Physical Verification (PV) to lead physical verification and signoff activities for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive DRC, LVS, ERC, ANTENNA, and reliability verification closure while collaborating closely with Physical Design, Layout, Foundry, and CAD teams to enable high-quality and timely tape-outs. This role requires deep expertise in signoff methodologies, debugging complex violations, and driving automation and process improvements. 

What You’ll Do 

• Lead block-level and full-chip physical verification and signoff activities for advanced SOC designs. 

• Drive DRC, LVS, ERC, ANTENNA, density, and reliability closure using industry-standard signoff methodologies. 

• Debug and resolve complex physical verification issues in collaboration with Physical Design, Custom Layout, and Foundry teams. 

• Develop and maintain scalable PV automation flows, rule decks, and regression infrastructure. 

• Analyze and resolve manufacturing and reliability challenges including EM/IR, latch-up, and ESD-related issues. 

• Support hierarchical verification, tape-out execution, and final GDS signoff deliverables. 

• Collaborate with CAD and EDA vendors for tool qualification, flow enhancement, and issue resolution. 

• Mentor junior engineers and contribute to methodology development and best practices. 

What We’re Looking For 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 

• 10+ years of experience in physical verification and signoff for ASIC/SOC designs. 

• Strong expertise in DRC, LVS, ERC, ANTENNA, density checks, and debugging methodologies. 

• Hands-on experience with industry-standard tools such as Calibre, ICV, Pegasus, or equivalent verification platforms. 

• Good understanding of physical design flow, layout concepts, process technologies, and manufacturing requirements. 

• Experience with advanced technology nodes including 7nm/5nm/3nm designs. 

• Strong scripting and automation skills using Tcl, Python, Perl, or Shell. 

• Excellent analytical, debugging, communication, and technical leadership skills. 

Good to Have 

• Experience with reliability verification including EMIR, ESD, and latch-up analysis. 

• Exposure to chiplet-based designs, 3D ICs, and advanced packaging technologies. 

• Knowledge of foundry tape-out processes and signoff qualification requirements. 

Success in This Role Looks Like 

• Successful closure of physical verification signoff for complex SOC tape-outs with high quality. 

• Fast and efficient resolution of physical verification and manufacturing violations. 

• Improved PV methodology scalability, automation, and execution efficiency. 

• Strong technical leadership and mentoring contributions across engineering teams.