Senior Engineer – Physical Verification (PV)

Role Overview 

We are looking for a highly motivated Senior Engineer – Physical Verification (PV) to join our Physical Design team. In this role, you will be responsible for driving block-level and full-chip physical verification signoff for advanced-node SoC designs. You will work closely with Physical Design, Layout, and Foundry teams to ensure high-quality and timely tapeouts. The role requires strong expertise in DRC/LVS methodologies, debugging complex violations, and improving PV automation flows. 

What You’ll Do 

• Perform block-level and full-chip Physical Verification including DRC, LVS, ERC, antenna, and density checks 

• Drive PV closure and debug complex violations in collaboration with Physical Design and Layout teams 

• Execute hierarchical and flat verification methodologies for advanced-node designs 

• Develop and maintain PV runsets, automation scripts, and signoff flows 

• Analyze foundry rule decks and ensure design compliance with process requirements 

• Optimize verification runtime, memory usage, and turnaround time 

• Support tapeout activities and ensure clean signoff delivery 

What We’re Looking For 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline 

• 5+ years of hands-on experience in Physical Verification or Physical Design signoff 

• Strong understanding of DRC, LVS, ERC, antenna, and density verification concepts 

• Hands-on experience with Mentor Calibre and exposure to Synopsys ICV is a plus 

• Good understanding of CMOS fundamentals, layout effects, and advanced-node design rules 

• Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow development 

Good to Have 

• Experience with advanced technology nodes such as 7nm, 5nm, or below 

• Exposure to FinFET technologies and multi-patterning design rules 

• Knowledge of reliability checks such as ESD, latch-up, and parasitic extraction/debug 

Success in This Role Looks Like 

• Achieving clean PV signoff with minimal iterations and timely tapeout support 

• Efficient debugging and closure of complex DRC/LVS violations 

• Improved verification productivity through automation and methodology enhancements 

• Strong collaboration across cross-functional teams leading to successful project execution