Develop and execute test plans for RTL designs using SystemVerilog and UVM while maintaining testbenches and test cases. Collaborate with internal teams and external vendors to debug designs, track coverage metrics, and ensure high-quality verification delivery.
The Physical Design Lead will own all physical design activities from RTL handoff through GDSII delivery, including floorplanning, PnR, and timing closure. They will also provide technical leadership and mentorship to the team while collaborating across functional groups to ensure high-performance silicon delivery.
