You will own the end-to-end architecture of the agent harness, including the agent loop, memory, permissions, and orchestration layers. Additionally, you will build evaluation suites and ensure reliable tool use across various AI models.
The Staff Physical Design Engineer will drive block-level and top-level physical implementation, including floor-planning, placement, and routing. They will also manage timing closure, power grid verification, and collaborate with foundry teams to ensure successful tapeout.
The Technical Program Manager will drive execution across embedded software workstreams, ensuring alignment between firmware, drivers, hardware, and silicon teams. They will own the end-to-end program plan from architecture through bring-up and customer deployment while managing cross-team dependencies and risks.
Lead end-to-end solution design, performance benchmarking, and system-level tuning for key verticals on EnCharge platforms. Proactively engage with customers and partners to optimize AI application performance and drive strategic product adoption.
The Lead DFT Engineer will architect the end-to-end testing strategy for complex SoCs, focusing on manufacturability and reliability for edge-to-cloud applications. This role involves leading post-silicon validation, collaborating with cross-functional teams, and implementing advanced test methodologies like MBIST and ATPG.
Drive the full-chip physical assembly and signoff of large-scale SOCs from floorplan to tapeout. Architect hierarchical physical verification flows and resolve complex bottlenecks to ensure optimal power, performance, and area.
Develop and optimize automated RTL-to-GDSII and timing signoff flows using Cadence Innovus and Tempus. Collaborate with Physical Design and STA leads to reduce turnaround time and improve PPA targets for AI accelerators.
Research and implement state-of-the-art techniques to accelerate AI inference and optimize model quality on custom silicon. Build fine-tuning pipelines and benchmarking frameworks to characterize tradeoffs between latency, throughput, and power consumption.
The role involves architecting and implementing optimizations for AI model execution on graph compilers to maximize hardware utilization and reduce latency. You will collaborate with hardware architects and researchers to convert high-level AI models into efficient intermediate representations for inference accelerators.
Define and develop the specifications and micro-architecture for key NPU modules, including in-memory compute and memory orchestration units. Collaborate with hardware and software teams to optimize AI accelerator performance for workloads like LLMs and CNNs.
The Senior Emulation Engineer will set up and maintain emulation platforms while adapting SoC designs for validation. They will collaborate with design and software teams to debug architectures, optimize workloads, and support early software bring-up.
The AI Compiler Engineer will architect, design, and implement optimizations for AI model execution on graph compilers. They will collaborate with hardware architects and AI researchers to enhance performance and enable efficient model deployment.
