sagar girawale

I am currently employed as a DFT Engineer at Google since June 2025. Before joining Google, I worked with Qualcomm India Private Limited as a DFT Lead, where I accumulated more than eight years of experience in the semiconductor industry. My professional journey includes extensive experience in Design for Testability (DFT), covering Scan, MBIST, BSCAN architectures, ATPG, silicon bring-up, and post-silicon debug, with exposure to advanced technology nodes such as 6nm, 14nm, and 28nm. Academically, I hold a Master’s degree in Electronics Design Technology from a Government of India institute and a Bachelor’s degree in Electronics and Communication Engineering. I value integrity, responsibility, and continuous learning in both my professional and personal life. Regards, Sagar Babasaheb Girawale