Physical Design

This role is for one of the Weekday's clients

Min Experience: 6+ years

Location: India
JobType: full-time

We are seeking an experienced Physical Design Engineer to drive the complete RTL-to-GDSII implementation flow for complex ASIC/SoC designs. The ideal candidate should have strong expertise in block- or chip-level physical design, timing closure, power optimization, and signoff using industry-standard EDA tools on advanced technology nodes.

Requirements

Key Responsibilities

• Execute the complete Physical Design flow from Netlist to GDSII.
• Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Drive timing closure while meeting PPA (Performance, Power, and Area) targets.
• Perform congestion analysis and optimize placement and routing.
• Analyze and fix setup/hold timing violations across all design corners and modes.
• Perform physical signoff including DRC, LVS, IR Drop, EM, and antenna checks.
• Collaborate with RTL, DFT, STA, and Packaging teams to achieve successful tape-out.
• Debug and resolve implementation issues while ensuring design quality.
• Support ECO implementation and timing closure activities.
• Ensure successful tape-out on advanced technology nodes.

Mandatory Skills (Deal-Breakers)

Candidates must have the following skills:

• 6+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong experience in complete RTL-to-GDSII implementation flow.
• Expertise in:
• Floorplanning
• Power Planning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Physical Verification
• ECO Implementation
• Strong timing closure experience with setup and hold optimization.
• Hands-on experience with Cadence Innovus.
• Experience using Synopsys ICC2 is an added advantage.
• Strong knowledge of Static Timing Analysis (STA) concepts.
• Experience with IR Drop, EM Analysis, Crosstalk, Noise, and Signal Integrity.
• Hands-on experience with Calibre for DRC/LVS signoff.
• Experience with advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, 12nm, 16nm, and FinFET.
• Good understanding of low-power implementation techniques (UPF/CPF).
• Experience in block-level or chip-level tape-out.
• Strong debugging and problem-solving skills.

Good-to-Have Skills

• Experience with Fusion Compiler implementation flow.
• Hands-on experience with Synopsys PrimeTime and PrimeTime-SI.
• Experience using RedHawk or Voltus for Power Integrity analysis.
• Knowledge of Formality and logical equivalence checking.
• Experience with hierarchical SoC implementation.
• Scripting skills in TCL, Python, or Perl.
• Exposure to multi-voltage and multi-power domain designs.
• Experience with CPU, GPU, AI/ML, Networking, Mobile, Automotive, or High-Performance Computing (HPC) SoCs.
• Familiarity with advanced packaging technologies such as 2.5D/3D ICs.
• Prior customer-facing or offshore/on-site collaboration experience.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• Excellent analytical, debugging, and communication skills.
• Ability to work independently and collaboratively in a fast-paced semiconductor development environment.

Must-have skills

Innovus, floorplanning

Good-to-have skills

STA, Placement