The Verification Engineer will develop and maintain robust RTL verification environments using UVM to ensure the functionality and quality of complex digital designs. They will also execute coverage-driven verification plans and collaborate with RTL design engineers to debug issues and drive verification to closure.
The Senior DFT Verification Engineer will develop and execute coverage-driven verification plans to ensure the quality and functionality of ASIC DFT logic. They will collaborate with design and manufacturing teams to implement test cases, debug complex issues, and support post-silicon test bring-up.
The SerDes Validation Lead will own the physical-layer implementation, configuration, and post-silicon validation of ultra-high-speed data links. They will collaborate with cross-functional teams to tune equalization parameters and ensure stable system-level performance.
You will own the physical implementation of complex blocks and subsystems from synthesized netlist through signoff. Additionally, you will develop implementation strategies, drive timing closure, and provide technical leadership across the physical design team.
