System Design Engineer (Senior/Staff/Senior Staff)

THE COMPANY
Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn). 
 
THE ROLE

We are seeking a highly skilled and experienced System Design Engineer (Modelling & Architecture) to play a key role in architecting and validating high-performance serial links and data-converter systems for our state-of-the-art chiplet solutions.

You will directly shape the system architecture and behavioural models of customer-facing IP, driving early design decisions, performance exploration, and architectural trade-offs across SerDes, ADC/DAC, and PLL subsystems.

This role is ideal for engineers with strong modelling expertise and system-level thinking, who enjoy bridging architecture and implementation in a fast-moving, high-impact environment.

Hiring Manager: Christian Borelli, Founder and CSO

KEY RESPONSIBILITIES

System Architecture & Modelling:
Define and develop system-level architectures and behavioural models for high-speed links and mixed-signal subsystems, including SerDes, ADCs, DACs, and PLLs.

High-Level Modelling (MATLAB / Simulink):
Build and maintain accurate system models in MATLAB/Simulink to evaluate performance, explore trade-offs, and guide design decisions across noise, jitter, bandwidth, and power.

SerDes System Modelling:
Develop end-to-end link models including channel, equalization (FFE/DFE), jitter budgets, and clock and data recovery (CDR) behaviour.

ADC/DAC Modelling & Calibration:
Model data converter architectures and implement advanced calibration algorithms (e.g. background calibration, mismatch correction, linearity enhancement), assessing system-level impact on ENOB, SFDR, and dynamic performance.

PLL & CDR Behavioural Modelling:
Develop behavioural models for PLLs and CDR loops, including phase noise, jitter transfer, loop dynamics, and locking behaviour.

Cross-Domain Collaboration:
Work closely with circuit designers, digital teams, and system architects to translate system requirements into block-level specifications and ensure model-to-silicon correlation.

Performance Analysis & Optimization:
Analyze system performance and identify architectural improvements across latency, power, robustness, and scalability.

Verification Strategy Support:
Contribute to system-level verification strategies and support correlation between behavioural models, RTL, and silicon measurements.

Technology & Competitive Awareness:
Stay current with industry trends in high-speed interfaces, data converters, and chiplet-based architectures, including benchmarking against competitive solutions.

Documentation & Knowledge Transfer:
Produce clear and structured documentation of models, assumptions, and architectural decisions to enable efficient collaboration and reuse.

WHAT WE’RE LOOKING FOR
Must-have Technical Skills:

• M.S. or Ph.D. in Electrical Engineering or related field
• 8–12+ years of experience in system design and modelling of high-speed or mixed-signal systems
• Strong expertise in SerDes system architecture and modelling
• Proven experience with MATLAB and Simulink for system-level modelling
• Solid understanding of ADC/DAC architectures and calibration techniques
• Experience in PLL and CDR modelling, including jitter and loop dynamics
• Good understanding of mixed-signal implementation constraints in advanced CMOS nodes
• Familiarity with link-level metrics: BER, eye diagrams, jitter budgets, equalization techniques
• Ability to bridge system modelling with circuit and RTL implementation

Nice-to-have:

• Experience with UCIe or chiplet-based architectures
• Exposure to behavioural modelling in SystemVerilog or real-number modelling (RNM)
• Prior silicon correlation or lab validation experience

Soft & Professional Skills:

• Clear, structured communication in professional English
• Strong system-level thinking and abstraction capability
• Collaborative, cross-functional mindset
• Ability to mentor and guide junior engineers
• High ownership and accountability
• Curious and proactive approach to problem-solving

 
OUR CULTURE
We’re a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere! 

• Our values are our north star: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.
• Connected, even remotely: We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.
• High ownership, real impact: Everyone contributes directly to customer-facing IP. Your work doesn’t disappear into layers of management – it ships.
• How we work: We move fast but thoughtfully, communicate openly, and balance autonomy with support. Technical decisions are debated openly and grounded in data, trade-offs, and first-principles thinking.

 
WHY JOIN US

• Remote-first flexibility – work from anywhere, with flexible hours
• Equipment & setup – we’ll provide the tools you need to succeed
• High-impact projects – design real analog IP used in customer silicon
• Supportive team culture – a dedicated manager and a team of colleagues ready to help
• Competitive, transparent compensation – adjusted for your location and engagement model
• Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

RECRUITMENT PROCESS

1. Founder Call (30 min) – mutual introduction and interest alignment
2. Technical Interview (60 min)  –  fundamentals, reasoning, and problem-solving
3. Presentation (45 min) – short presentation on a topic of your choice, to assess clarity, structure, and confidence in presenting your work
4. HR & Culture Call (45 min) – values, collaboration style, and ways of working
5. Offer & Next Steps (30 min) – offer walkthrough, alignment on details, and next steps, discussed in a final call with the founder.

If you don’t meet every requirement but feel excited about the role, apply anyway. We value curiosity, integrity, and potential as much as experience.