AMS Verification Engineer (Senior/Staff/Senior Staff/Principal)

THE COMPANY
Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn). 
 
THE ROLE

We are looking for an AMS Verification Engineer to lead the verification strategy for high-speed SerDes IP and complex mixed-signal subsystems. In this role, you will own end-to-end AMS verification planning and execution, from early architecture and modelling through to signoff. You will work closely with analog design, digital RTL, architecture, and validation teams to ensure that our SerDes IP is robust, well-verified, and ready for integration into advanced communication systems.
This role is ideal for a senior verification engineer with deep SerDes expertise, strong mixed-signal methodology knowledge, and the ability to provide technical leadership across projects. You should be comfortable working across abstraction levels, from behavioural and RNM models to AMS simulation, protocol-level verification, and silicon correlation where applicable.

Hiring Manager: Christian Borelli, Founder and CSO

KEY RESPONSIBILITIES

• AMS Verification Strategy: Own and drive the AMS verification strategy for high-speed SerDes IP from concept through to signoff, ensuring verification plans are technically rigorous, scalable, and aligned with project goals.

• Verification Environment Development: Architect, develop, and maintain advanced verification environments using SystemVerilog, UVM, and UVM-AMS methodologies.

• Mixed-Signal Modelling: Develop, integrate, and validate behavioural models, including RNM, Verilog-AMS, and wreal models, balancing simulation accuracy with performance and scalability.

• Protocol & Feature Verification: Lead verification of key SerDes behaviours and features, including link training, initialization, adaptation, BIST, PRBS, loopback, error injection, and robustness scenarios.

• Debug & Root-Cause Analysis: Analyze and debug complex mixed-signal issues involving timing, jitter, noise, clocking, protocol behaviour, and digital/analog interaction.

• Coverage & Signoff: Drive functional, assertion-based, and coverage-driven verification, including regression planning, metrics tracking, corner cases, PVT, stress, and performance verification.

• Cross-Functional Collaboration: Work closely with analog design, digital RTL, architecture, system modelling, and validation teams to align verification strategy with design intent and implementation constraints.

• Verification Strategy Support: Contribute to system-level verification strategies and support correlation between behavioural models, RTL, and silicon measurements.

• Technical Leadership: Mentor and technically guide junior verification engineers, helping raise the overall quality, consistency, and maturity of verification practices across the team.

• Silicon Correlation & Bring-Up Support: Contribute to silicon bring-up, post-silicon debug, and model-to-silicon correlation activities where applicable.

WHAT WE’RE LOOKING FOR
Must-have Technical Skills:

• M.S.or Ph.D. in Electrical Engineering, Electronics Engineering or a related field
• 10+ years of experience in AMS verification, mixed-signal verification, or high-speed interface verification
• Strong hands-on experience with SystemVerilog, UVM, and UVM-AMS
• Strong expertise in Verilog-AMS, AMS RNM, and wreal modelling
• Experience with mixed-signal simulation environments such as Cadence Xcelium AMS, Synopsys VCS AMS, or Siemens Questa ADMS
• Deep understanding of high-speed SerDes architectures, including TX/RX data paths, PLLs, CDRs, clocking, equalization, jitter, and signal integrity concepts
• Strong experience verifying SerDes protocols, especially USB and DisplayPort
• Experience with at least some of the following protocols: PCIe, Ethernet, HDMI, MIPI, SATA
• Experience with multi-lane, multi-rate, and multi-protocol SerDes IP
• Strong debugging skills in complex mixed-signal simulation environments
• Experience with functional verification, assertion-based verification, coverage-driven verification, regression flows, and verification metrics
• Proficiency in scripting and automation using Python, Perl, or Tcl
• Ability to automate regression flows, result analysis, reporting, coverage tracking, and verification dashboards
  
  

Nice-to-have:

• Experience correlating MATLAB or Python system models with behavioural/RNM models and      transistor-level simulations
• Experience supporting silicon bring-up, post-silicon debug, and lab correlation
• Experience working on customer-facing SerDes IP or reusable mixed-signal IP platforms
• Exposure to chiplet-based architectures or high-speed interconnect standards
• Experience defining verification methodology improvements across multiple projects or      teams

Soft & Professional Skills:

• Clear, structured communication in professional English
• Strong system-level thinking and abstraction capability
• Collaborative, cross-functional mindset
• Ability to mentor and guide junior engineers
• High ownership and accountability
• Curious and proactive approach to problem-solving

 
OUR CULTURE
We’re a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere! 

• Our values are our north star: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.
• Connected, even remotely: We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.
• High ownership, real impact: Everyone contributes directly to customer-facing IP. Your work doesn’t disappear into layers of management – it ships.
• How we work: We move fast but thoughtfully, communicate openly, and balance autonomy with support. Technical decisions are debated openly and grounded in data, trade-offs, and first-principles thinking.

 
WHY JOIN US

• Remote-first flexibility – work from anywhere, with flexible hours
• Equipment & setup – we’ll provide the tools you need to succeed
• High-impact projects – design real analog IP used in customer silicon
• Supportive team culture – a dedicated manager and a team of colleagues ready to help
• Competitive, transparent compensation – adjusted for your location and engagement model
• Learning & growth – AI–DLP sessions, technical deep dives, and peer-led knowledge sharing that build both technical depth and system-level perspective

RECRUITMENT PROCESS

1. Founder Call (30 min) – mutual introduction and interest alignment
2. Technical Interview (90 min)  –  fundamentals, reasoning, and problem-solving
3. Presentation (60 min) – short presentation on a topic of your choice, to assess clarity, structure, and confidence in presenting your work
4. HR & Culture Call (45 min) – values, collaboration style, and ways of working
5. Offer & Next Steps (30 min) – offer walkthrough, alignment on details, and next steps, discussed in a final call with the founder.

If you don’t meet every requirement but feel excited about the role, apply anyway. We value curiosity, integrity, and potential as much as experience.