Design and integrate production-quality digital IP and SoC subsystems, focusing on high-speed interconnects and chiplet-centric architectures. Collaborate across architecture, verification, and physical design teams to ensure performance, power, and area targets are met.
Drive the physical implementation of digital blocks and full-chip designs from netlist to tapeout. This includes owning floorplanning, timing closure, and physical signoff while collaborating with RTL and DFT teams.
Own signal and power integrity, as well as package and power delivery network co-design across chip, package, and board interfaces. Collaborate with cross-functional teams to ensure robust high-speed links and stable power delivery from architecture through tapeout.
Ensure the functional correctness and tapeout readiness of complex IPs and SoCs by building scalable verification environments. This includes owning the process from testplan creation through signoff, including regressions and coverage closure.
Design and deliver high-performance analog and mixed-signal circuits from requirements definition through to silicon signoff. Collaborate cross-functionally to support silicon bring-up, debug, and the implementation of design fixes.
Define and scale EDA infrastructure and design signoff methodologies to enable efficient silicon delivery. Own end-to-end implementation flows and build automated infrastructure for synthesis, STA, and physical verification.
Lead the end-to-end talent acquisition life cycle and employer branding efforts specifically for semiconductor roles. Develop HR strategies including onboarding plans, upskilling modules, and retention programs for R&D engineers.
