Own the end-to-end power-delivery design from on-die grids to PCB PDN and lead advanced packaging architecture for 2.5D/3D systems. Collaborate with cross-functional teams to ensure signal and power integrity targets are met for AI accelerators.
Axelera AI
7 Remote Job Openings at Axelera AI
Lead the Field Application Engineering function across EMEA, managing technical customer engagements from hardware bring-up to production deployment. Build and scale a regional FAE team while acting as the technical bridge between customers and global R&D teams.
Lead the Field Application Engineering function in Taiwan, providing hands-on technical support for the integration and deployment of the Metis AI Platform. Build and manage a regional FAE team while collaborating with global R&D and Product teams to drive design wins.
Establish and lead the AI Infrastructure Systems division to deliver next-generation accelerator silicon in datacenter-class form factors. This includes owning the technical roadmap, building a multidisciplinary engineering team, and managing end-to-end product delivery from concept to mass production.
The Quality Manager will own the end-to-end quality function within Operations, managing everything from supplier qualification and NPI to production and field returns. They will establish robust quality systems, drive cross-functional alignment, and serve as the primary quality authority for the organization.
This role involves leading and scaling the silicon logical design team, driving the translation of specifications into high-quality RTL implementations, and owning the end-to-end logical design execution for one or more SoCs from concept through tape-out. The director will also partner with cross-functional teams to ensure robust designs and define best practices for RTL quality and reviews.
As a Logical Design Engineer, you will collaborate with cross-functional teams to implement advanced micro-architectures for AI products. Your role will involve ensuring high quality and performance while integrating various IPs into the top-level SoC.
