Remote ASIC Verification Engineer

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Posted 11 days ago United States Salary undisclosed
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Job Description

Mid size startup, Series C funding, working on Autonomous AI chips/ image processing for cars. Great salary, benefits, and Equity options.

This Jobot Job is hosted by: Barrett Davis
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A bit about us:

Based in San Jose, CA, we are the leading developer of state-of-the-art camera video processors! We have been named the design company of 2018 by Semiconductor TODAY magazine for the automotive and consumer industries. Backed by over 120 patents we have invested in our long-term success by committing to the development of the future, big-name clients such as Lexus, Audi, and Ferrari.

Why join us?
  • Competitive Base Salary
  • Extremely Competitive Full Benefits Package
  • Flexible Work Schedules
  • Accelerated Career Growth

Equity options

Job Details

ASIC Verification Engineer, UVM from existing or scratch, System Verilog
Onsite in San Jose California, or Toronto Canada.

Full job description is below.

Develop test strategies to verify next-generation camera processors
Develop and review block and chip-level verification environments and test plans
Work closely with design engineers to develop test benches and test plans to meet coverage goals
Participate in selecting best in class 3rd party protocol verification IP
Help enhance the overall DV methodology by analyzing 3rd party verification tools
Debug failures in simulation and collaborate with designers in identifying root-cause issues
Develop a tests that will help achieve functional safety goals that meet ISO26262 compliance
Work with the systems and software teams on emulation platforms
Participate in the bring-up and debug of the device prototype
Provide support to the Product Engineering team to meet all validation and qualification goals for the product
MINIMUM QUALIFICATIONS

BSEE/BSCE/BSCS
5 years of industry experience in design verification
Experience with test planning, test bench architecture, and assertions
Constrained random verification experience with SystemVerilog using UVM
Coverage driven verification (code/functional/assertion coverage)
Strong programming skills in C/C++ and scripting experience with Python/Tcl/Perl

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